Electronic circuits generally include current mirrors as a basic building block in order to transfer current, to provide bias current sources which may further provide bias voltage sources. Current mirrors may also exist as part of the signal path rather than the bias path, such as in current feedback amplifiers. A current mirror is a circuit which, ideally, has zero input impedance to receive an input bias current and infinite output impedance, so that current output remains a fixed function of current input (stiff), regardless of variations in output load, variations in output voltage or fluctuations in applied power source; the current mirror is said to mirror current accurately. To achieve the desired large output impedance typically requires some form of cascoding (series stacking of transistors) in order to multiply the output resistance. The need to do this becomes increasingly more important, as process minimum geometries continue to shrink and output resistances of short channel length devices continue to drop. An undesirable side effect of cascading, however, is that output voltage swing (range of output voltage for which the output resistance remains high) becomes limited due to the need to maintain additional series-connected devices in their active (e.g., saturated for MOS devices) operating regions. This problem of loss of voltage range is further compounded by a trend toward lower voltage power supplies in small geometry processes. For example, losing 1.0 V of output range can be significant, resulting in total output voltage swings of less than 1.5 V, where a 2.5 V voltage supply is involved. The problem worsens with portable electronic devices, personal medical electronics, and wireless applications where supply voltage ranges are now typically lower than 2.5 V.
First some terminology and introduction is needed. As described in the Johns & Martin reference, “Analog Integrated Circuit Design”, Chapter 1, (1997 John Wiley & Sons)), a MOS transistor operates in its saturated region when its drain-source voltage Vds is at least as great as its gate (gate-source) voltage Vgs minus its threshold voltage Vt (i.e., the voltage at which the inversion layer is formed) and Vgs is greater than Vt. The minimum value of the source-drain voltage Vds that satisfies these relationships is termed the overdrive voltage Vov of the transistor, and can be expressed as follows: Vov=Vgs−Vt where Vov is the minimum Vdsat saturation voltage of the transistor. The Vgs voltage is an applied voltage that is typically a function of the circuit design and power supply voltages; it is extrinsic to the transistor. There is a well known “body effect” where the threshold voltage Vt, intrinsic to the transistor, depends on whether the bulk (backgate) terminal is at the same voltage as the source terminal of the transistor. In many kinds of MOS technologies, there is no ability to directly short together the bulk terminal and the source terminal, to conveniently set the voltage of the two terminals to be the same. The value of Vt increases when the two terminals are not at the same voltage. Therefore, in some technologies, the value of Vov and Vdsat may be dependent on the body effect, along with other conditions such as temperature, current density, etc. There is a square law relationship between a drain current Id through the transistor and its node voltages when a MOSFET is operating in the active region (Johns & Martin):Id=u CoxW(Vgs−Vt)2(1+λ(Vds−(Vgs−Vt))/(2L)
Where Vgs is the gate-source voltage, Vds is the drain-source voltage, W is the physical gate width, L is the effective gate length, u is the mobility of electrons near the silicon surface, Cox is the gate oxide capacitance per unit area, and λ is an output impedance constant. The conditions for a transistor to be in the active region are Vgs>Vt and Vds>Vov, so that a current Id flows through the transistor. A graphical plot of the above equation shows Id is relatively constant with respect to Vds, in the active region condition. Constancy of Id is highly desirable for current source and current mirror circuits; so transistors being in the active region is highly desirable. For transistors of a well designed current mirror circuit operating under such conditions, the output resistance would be high and the current generated would be substantially constant.
A cascode current mirror is shown in FIG. 1a, which will be termed a compound cascode current mirror (CCCM, 10) in this disclosure. It was introduced in U.S. Pat. No. 4,477,782, (FIG. 2) and Ysividis & Antognetti “Design of MOS VLSI Circuits for Telecommunications”, p. 560 (1985 Prentice Hall). In CCCM 10, transistors M1 and M2 are the mirror transistors and M3 and M4 are the cascode transistors cascoding (coupled in series with) M1 and M2, respectively. Transistors M1 and M3 form the input leg coupled to the input current bias node; M2 and M4 form the output leg coupled to the output node. In addition to the above references, general background information relating to the cascode configuration and current mirror circuits is also given in Gray & Meyer, “Analysis and Design of Analog Integrated Circuits”, Chapters 1 and 4 (1993 John Wiley & Sons). Biasing schemes to enable the CCCM to operate reasonably properly are provided in the above references and also in other patents, e.g. U.S. Pat. No. 6,617,915 B2. Further example biasing schemes are shown in FIGS. 1a and 1b elements 20, 30, and 40. Generally the gates of the cascode transistors are biased at some voltage, though one example also attempts to inject a current at the connection (intermediate) node between M1 and M3 of the input leg.
FIG. 1a illustrates a CCCM 10 implemented using N-channel MOS transistors where the prior art biasing schemes have attempted to improve the output swing of the CCCM on the output leg. However, during the operation of a circuit, the environmental conditions (e.g. supply voltages, temperature, pressure) typically will vary. During the manufacture of the circuit, there will also be technology process variations, mismatches and process corner variations. These conditional variations will cause the performance of the CCCM to not mirror current accurately and vary in a way that is not solved by the prior art biasing schemes. For example, the transistors of the CCCM may not operate in the optimal active region, the range of output voltage swing will vary, and so on. The prior art bias schemes do not bias the CCCM to have the lowest saturation voltage (just entering the active region) across process corners. The prior art schemes also tend to work poorly when the cascode and mirror transistors are of different type (technology kind) transistors. Most process technologies offer a variety of transistors even if they are of the same N or P flavor, e.g. high or low Vt Nmos, thick or thin gate oxide, drain extended, high or low breakdown voltage, and so on. It is generally beneficial to use a different kind of transistor for the cascode transistors as opposed to the mirror transistors in the CCCM in order to allow for, say, more headroom within a limited supply voltage range or lowered parasitic capacitance dependent on the kind of transistor used. The prior art schemes also tend to be more optimal for transistors with long gate lengths (L) wherein the gate W/L ratio then may become low enough to where the transistor models are less reliable, a problem during the design phase of the circuit.
By way of specific background to the preceding, FIG. 1a elements 20 and 30 illustrate a schematic of a prior art biasing circuits to allow for maximum output voltage swing in a CMOS cascode current mirror. Element 20 by Vittoz generates a bias voltage VB for the gate of the cascode transistors M3 and M4 in the CCCM element 10. Vittoz uses a diode connected transistor M5 whose Vgs is shifted upwards by split transistors M6 and M7, with M5-M7 all being the same kind of transistors. Element 30 by Vincence et al. generates the bias voltage VB using a diode-connected split transistors MA5 and MB5; the effective Vgs of this pair is shifted upwards by the circuit formed by MB7, MA7 and M6; all of these transistors are all the same kind. The same current I runs down each leg of the either the Vittoz or the Vincence et al. bias circuits. These biasing schemes are for the case where M2 and its cascode transistor M4 in the CCCM circuit 10 are of the same kind and the schemes assume that M2 has high gain.
FIG. 1b illustrates another example of a cascoded current source which maximizes the output voltage swing, which is popularly shown in college textbooks, such as Gray & Meyer. The output IOUT of the current source is formed by transistors Q2 and its cascode Q4. The actual mirror transistors are Q1 and Q2 which need to have comparable Vgs and comparable Vds (gate-source and drain-source voltage) in order to provide good mirrored-current matching (Iout=I1). The drain of Q2 is maintained at VDsat, the edge of the active region. Diode connected Q1 and Q3 set up voltage biases at the gates when a current I1 traverses leg A. The voltage bias input to the source follower formed by Q5 and Q6, leg B. By selecting a particular ratio of transistor sizes for circuit 40, Q2 may be biased at the edge of saturation. Although the output voltage Vout has improved voltage swing, the current matching suffers because the Vds voltage of Q1 and Q2 differ.
In view of the above issues, there arises a need to address the drawbacks of the prior art, as is achieved by the preferred embodiments described below.